Chemical Mechanical Planarization or Polishing (CMP) is a method of planarizing a semiconductor structure surface. CMP is typically carried out after forming a new layer on the surface of a semiconductor structure. As the size of features on semiconductor structures decreases, and the size of the wafers the semiconductor structures are formed on increases, the uniformity of planarization, both between wafers and across each wafer, has become more important.
Formation of shallow trench isolation (STI) structures in a semiconductor structure includes CMP. As part of forming a STI structure, a nitride layer is deposited on the semiconductor structure, a trench is formed in substrate, and subsequently an oxide layer is deposited on the structure (see, for example, U.S. Pat. No. 6,593,208). CMP is then used to remove excess oxide which is above the surface plane of the nitride, leaving oxide in the trench. CMP is then used for controlled removal of a portion of the nitride, to reduce pattern density effects.
Typically, the two CMP processes are carried out on separated platens, and even separate CMP system because different chemistries, and therefore different slurry compositions, are needed for each polish. For removing excess oxide, the CMP chemistry typically has a low oxide/nitride selectivity, while the chemistry used for controlled removal of a portion of the nitride has a reduced rate of nitride removal. The slurry composition used in the latter CMP step contains cerium oxide, water, and a surfactant that reduces the removal rate of nitride, all buffered to a pH of 4 (see, for example, H.-G. Kang, et al. “Dependence of pH, Molecular Weight, and Concentration of Surfactant in Ceria Slurry on Saturated Nitride Removal Rate in Shallow Trench Isolation Chemical Mechanical Polishing” Jpn. J. Appl. Phys., Vol. 44, No. 7A (2005) pp. 4752-4758). An example of this type of slurry is EKC STI2100B™ (EKC Technology, Danville Calif., a part of DuPont).
Previous attempts to develop a single chemistry or single step CMP process with high selectivity to nitride have resulted in either a low initial removal rate of oxide, poor residual nitride control or a high number of wafer defects. Specifically, the defects seen with this approach include a pattern density defect, commonly referred to as a dip defect, shown in FIG. 1. Dip defects are the largest contributor to the total defect count, accounting for about 80-90% of the total defects. It is believed that dip defects are caused by the EKC STI2100B™ attacking field oxide locally after the first CMP step is completed.